This application claims the priority benefit of Taiwan application serial no. 88106504, filed Apr. 23, 1999. The present application is related to copending filed on the same date as this application, entitled xe2x80x9cDELAYED TRANSACTION METHOD AND DEVICE USED IN A PCI SYSTEMxe2x80x9d by LAI et al., currently pending.
1. Field of Invention
The present invention relates to a method for controlling peripheral components. More particularly, the present invention relates to the transfer of data via a peripheral component interconnect (PCI) bus.
2. Description of Related Art
FIG. 1 shows a conventional computer architecture that uses a PCI bus. As shown in FIG. 1, a PCI host bridge 12 is coupled to a PCI bus 14. The PCI bus 14 is capable of coupling to a number of PCI compatible master controllers, which are embedded within a peripheral component. The peripheral components may include, for example, a graphic adapter 16a, an expansion bus bridge 16b, a LAN adapter 16c and SCSI host bus adapter 16d. Each master controller within these peripheral components is capable of sending out a request (REQ) signal to the arbiter within the PCI bridge 12 via the PCI bus 14 requesting for data transfer through the PCI bus. On receiving the request (REQ), the PCI bridge 12 can issue a grant (GNT) signal to the master controller accepting its use of the PCI bus 14.
Data transfer between different PCI compatible components (for example, a master controller and the north bridge of a computer chipset) can be realized through an interface control signal described below. In the beginning, a cycle frame (FRAME) is transmitted from an initiator (possibly a master controller or a north bridge) signaling the initiation of a data accessing period. The sending of a FRAME signal implies that a data transaction through the PCI bus has begun. As long as the FRAME signal remains at a low potential, it means the data transaction is still under way. Soon after the FRAME signal is out, valid address will be set up on address bus lines AD during the address phase. At the same time, valid bus commands (meeting PCI specifications) will be sent from the command/byte enable (CBE [3:0]) lines so that the target device will notice the kind of data transaction demanded by the initiator. In general, the command/byte enable uses four bits on four lines to encode 16 commands, and relevant details can be found in the PCI specifications. After valid address is out, the requested data will be put on the address/data bus AD in the so-called data phase. In the meantime, byte enable signals corresponding to the encoded bus command will be sent through the CBE lines for data transmission. When the FRAME signal is finally terminated by the initiator, this implies either the last set of data is out, or data transmission is complete. During the data transmission phase, the initiator ready (IRDY) signal and the target ready (TRDY) signal work with each other for indicating the state of affairs in the initiator and the target device. The two synchronize with each other so that data transmission can be carried out smoothly. During a data read operation, putting up an IRDY signal implies the initiator is ready to receive data. During a data write operation, putting up a TRDY signal implies the target is ready to receive data. In addition, there is a stop (STOP) signal that can be set up by the target device requesting the initiator to cancel the current data transaction.
FIG. 2 is a timing diagram showing the sequence of events at a PCI bus interface during a read operation. A period within which the entire process of data transfer is carried out using a PCI bus is known as a bus transaction period 20. The bus transaction period 20 can be divided into an address phase 22 and several data phases such as 24a, 24b and 24c. Each data phase 24a/b/c can be further divided into a wait cycle 26a/b/c and a data transfer cycle 28a/b/c. Next, the operation of the PCI system is explained with respect to the various aforementioned controlling signals according to PCI specifications.
First, in cycle T1, the initiator will submit a FRAME signal indicating the start of a data transfer operation, and then a start address is submitted via the address/data bus AD for pin-pointing at a target device. At the same time, the CBE line will issue a read instruction. Thereafter, the CBE line will issue a byte enable signal. The byte enable signal is maintained throughout the entire data phase (including 24a, 24b and 24c). In cycle T2, the initiator will forward an initiator ready IRDY signal indicating data transfer can begin. If, at this moment, the target device is not ready yet, the initiator must wait until the target device is ready. The waiting period is known as a wait cycle 26a. Later, in cycle T3, the target device is ready and hence a target ready TRDY signal is issued by the target device. Therefore, during data transfer cycle 28a, data is read from the target device to the initiator. In cycle T4, the target ready TRDY signal is terminated signaling the end of data transfer. Next, the second set of data is being prepared while the wait cycle 26b of the second data transfer cycle 24b begins. In cycle T5, target ready TRDY signal is again issued implying that the second set of data is ready. When the initiator ready IRDY signal and the target ready TRDY signal are up during data transfer cycle 28b, the second set of data is transferred from the target device to the initiator. When the initiator could not read the incoming data fast enough, the initiator will terminate the initiator ready IRDY signal in cycle T6, for example. Since the target ready TRDY signal is still up, the wait cycle 26c is actually initiated by the initiator. As soon as the initiator is ready again, an initiator ready IRDY signal is submitted in cycle T7. Now, the initiator ready IRDY signal and the target ready TRDY signal are up again during data transfer cycle 28c, so the remaining third set of data are read from the target device to the initiator. Hence, the entire read operation is complete.
In the PCI specifications (for example, in version 2.2), a special type of data transfer mode commonly referred to as delayed transaction exists. The so-called delayed transaction is an operating sequence that is employed when the complete transfer of data could not be finished within the initial data phase. There are two main types of components that possibly require delayed transaction, namely, an input/output (I/O) controller and a bridging device. Usually, an I/O controller can process only one delay transaction at a time, whereas a bridging device can process a multiple of delayed transactions simultaneously thereby giving an improved system efficiency.
Conventional delayed transaction involves three cycles. First, the master controller will submit a request for using the PCI bus. Next, the target device will try to complete the operations requested by the master controller. Finally, the transaction is completed by the master controller. During the entire delayed transaction cycle, the master controller not only will continuously submit request signals, but will also seek out the current status of the target device through operations similar to polling. Thus, the PCI bus is fully occupied and hence unable to perform any other operations.
For a PCI system under the conventional delayed transaction mode, if a transaction needs to be re-tried, the master controller has to forward a request REQ signal to the PCI bus repeatedly. The master controller has to repeat the request REQ signal to the PCI bus until data are ready for transmission. Since the PCI bus is fully occupied when the master controller keeps putting up data requests, any other data transfer operations are impossible. Consequently, the PCI bus is very much underutilized.
In light of the foregoing, there is an urgent need to improve the degree of utilization of the PCI bus.
Accordingly, the present invention is to provide a method of conducting delayed data transaction on a PCI system capable of reducing the period within which the bus is occupied by a PCI compatible master controller so that system efficiency is improved.
A second aspect of the invention is to provide a method of conducting delayed data transaction on a PCI system whose target device is capable of acting like a master controller so that the target device can return the requested data to the requesting master controller automatically once the data is ready.
A third aspect of the invention is to provide a method of conducting delayed data transaction on a PCI system such that the target device is capable of generating a defer address and a defer identifier if the target device needs time to retrieve the requested data. Therefore, when the requested data is ready, the target device will be able to return the data to the requesting master controller correctly.
A fourth aspect of the invention is to provide a method of conducting delayed data transaction on a PCI system that can be implemented with appropriate hardware construction.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method of conducting delayed data transaction on a PCI system and its associated devices. The delayed data transaction is carried out using a PCI system to transmit data between an initiator and a responder. Both the initiator and the responder are coupled to a PCI bus. The delayed transaction in the PCI system includes a number of steps. To begin with, the initiator will send out a request to use the PCI bus so that data transmission can be conducted with the responder. If the responder accepts the request but unable to secure the requested data soon enough, the responder will generate a defer identifier that corresponds to the requesting initiator. Next, a stop signal and the defer identifier generated by the responder will be returned to the initiator. When the requested data is ready in the responder, the responder will forward the defer identifier again. The initiator picks up the defer identifier and prepares itself according to the defer identifier, and then data transmission between the initiator and the responder begins. The defer identifier further includes a defer address and a buffer identifier. The defer address corresponds to the initiator. The buffer identifier corresponds to one of the data transactions being processed inside the responder, and one of the functional units inside the initiator.
In a second embodiment of this invention, a method of conducting delayed data transaction on a PCI system is provided. The delayed data transaction is carried out using a PCI system to transmit data between a first initiator and a responder, and a second initiator and the same responder. The first initiator, the second initiator and the responder are all coupled to the PCI bus. The delayed transaction in the PCI system includes a number of steps. To begin with, the first initiator will send out a request to use the PCI bus so that data transmission can be conducted with the responder. If the responder accepts the request but unable to secure the requested data soon enough, the responder will generate a first defer identifier that corresponds to the requesting first initiator. Next, a stop signal and the first defer identifier generated by the responder will be return to the first initiator. Later, the second initiator also needs to have some data. Hence, the second initiator will send out a request to use the PCI bus so that data transmission can be conducted with the responder. If the responder accepts the request but unable to secure the requested data soon enough, the responder will generate a second defer identifier that corresponds to the requesting second initiator. Next, a stop signal and the second defer identifier generated by the responder will be returned to the second initiator. When the data requested by the first initiator is ready in the responder, the responder will forward the first defer identifier as the address of the respond transaction. The first initiator picks up the first defer identifier and prepares according to the first defer identifier, and then data transmission between the first initiator and the responder begins. Similarly, when the data requested by the second initiator is ready in the responder, the responder will forward the second defer identifier as the address of the respond transaction. The second initiator picks up the second defer identifier and prepares according to the second defer identifier, and then data transmission between the second initiator and the responder begins. The first defer identifier further includes a defer address and a buffer identifier such that the defer address corresponds to the first initiator while the buffer identifier corresponds to one of the data transactions being processed inside the responder. In addition, if the responder is unable to process the data request generated by the second initiator, the responder will generate an invalid defer identifier that corresponds to the second initiator. The invalid defer identifier will be returned to the second initiator informing the initiator to put up its request again.
In a third embodiment of this invention, a method of conducting delayed data transaction on a PCI system is provided. The delayed data transaction is carried out using a PCI system to transmit data between an initiator and a responder. Both the initiator and the responder are coupled to a PCI bus. The delayed transaction in the PCI system includes a number of steps. To begin with, the initiator will send out a first request to use the PCI bus so that data transmission can be conducted with the responder. If the responder accepts the first request but unable to secure the data requested by the first request soon enough, the responder will generate a first defer identifier that corresponds to the requesting first initiator. Next, a stop signal and the first defer identifier generated by the responder will be returned to the initiator. Later, the initiator needs to have some other data. Hence, the initiator sends out a second request to use the PCI bus so that data transmission can be conducted with the responder. If the responder accepts the second request but unable to secure the data requested by the second request data soon enough, the responder will generate a second defer identifier that corresponds to the second request of the initiator. Next, a stop signal and the second defer identifier generated by the responder will be returned to the initiator. When the data requested by the first request of the initiator is ready in the responder, the responder will forward the first defer identifier as the address of the transaction responding to the first request. The initiator picks up the first defer identifier and prepares according to the first defer identifier, and then data transmission between the initiator and the responder begins. Similarly, when the data requested by the second request of the initiator is ready in the responder, the responder will forward the second defer identifier as the address of the transaction responding to the second request. The initiator picks up the second defer identifier and prepares according to the second defer identifier, and then data transmission between the initiator and the responder begins. The first defer identifier further includes a defer address and a first buffer identifier, and the second defer identifier further includes a defer address and a second buffer identifier. The defer address corresponds to the initiator. The first defer identifier corresponds to a first data transaction within the responder, and the second defer identifier corresponds to a second data transaction within the responder. In addition, if the responder is unable to process the second data request generated by the initiator, the responder will generate an invalid defer identifier that corresponds to the second request of the initiator. The invalid defer identifier will be returned to the initiator informing the initiator to put up its second request again.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.